As is known in the art, one type of data storage system includes an interface disposed between a host computer/server and a back of disk drives. One such system is described in U.S. Pat. No. 6,651,130 entitled “Data Storage System Having Separate Data Transfer Section and Message Network with Bus Arbitration, inventor Robert Thibault, issued Nov. 18, 2003, assigned to the same assignee as the present invention, the entire subject matter thereof being incorporated herein by reference. As described therein, the system includes host computer/server controllers, or directors, disk controllers, or directors, and cache memory interconnected through a backplane printed circuit board. More particularly, disk directors are mounted on disk director printed circuit boards. The host computer/server directors are mounted on host computer/server controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk directors, host computer/server directors, and cache memory printed circuit boards plug into different slots of the backplane printed circuit board, as shown in FIG. 7 and as described in more detail in the above-referenced U.S. patent application Ser. No. 10/109,583. More particularly, each one of the director boards includes a plurality of director CPUs. For example, as described in the above-referenced U.S. Pat. No. 6,651,130 each director board includes four director CPUs.
One method used to test such system includes testing using a diagnostic code package. The diagnostic code is made of embedded code which resides on each tested director or memory printed circuit board, and of a script which resides on a computer, e.g., the PC which is connected to the system under test as described above. The diagnostics process is actually a set of tests which are executed on the printed circuit boards and their purpose is to verify the system is functioning properly and ready for the customer. The script on the PC is executing the tests on the boards by sending commands to each board; the results of the test are logged into text files on the PC.
It follows then that as the number of CPUs per director board increases, for example to a system wherein each director board has 8 CPUs and the system has 16 director boards, there are 128 log files created plus 4 more log files from environmental boards and a few logs generated by the script. A pair of such logs for a corresponding pair of director CPUs appears, for example, as follows:
%H>GO GIGETST / FLB_DCPU SPAWN TSTLOOP 10000 DMA_BGT SADD_BGT KKCS 7 ADDR 1B0951D00 LEN 10000%H>TASK START TIME: *00:28:16.81 10-28-03%H>anath6-4>%H>---[id # 00C9 Gigabit Ethernet Utilities & Tests]%H>%H>Gigabit Ethernet Utilities & Tests PASSED.%H>%H>TASK DONE%H>TASK END TIME: *00:29:01.35 10-28-03%H>GO GIGETST / FLB_DCPU SPAWN TSTLOOP 10000 ADMA_BGT NSIO_BGT KKCS 7 ADDR 1B0961D00 LEN 10000%H>TASK START TIME: *00:29:01.75 10-28-03%H>anath6-4>%H>---[id # 00C9 Gigabit Ethernet Utilities & Tests]%H>Data not appended3%H>T3::appnd_io_ink( ) returned erro%H>num_pckts=10000 last_rcv_cnt=10400 num_pckts_done=10800 num_pckts_to_be_sent=10000%H>Gig Ethernet Dual cpu Full Loopback test . . . FAILED Loop 0%H>%H>ERROR:ErrCode: 00C900070A0A000A Slot: 3 CPU: 11%H>ErrTime: *00:29:21.37 10-28-03%H>TaskStartTime: *00:29:01.75 10-28-03%H>Loop: 1 of 1 CLoop: 0 of 1%H>TestDesc: FIGE gigabit ethernet test%H>SubtDesc: Dual Cpu Synchronous Full Loopback Test%H>ErrGroup: FIGE lback Errs group%H>ErrDesc: Link cpu failed to complete I/O%H>%H>ErrDetail:%H>%H>* Link cpu failed to complete I/O:%H>------------------------------------------------------------------%H>%H>%H>* General Gige test information:%H>------------------------------------------------------------------%H>%H>Inner Loop:00000000%H>Packet Len:000005DC%H>Packet Num:00000001%H>Pckt Tx'd:00030000%H>Pckt Rx'd:00010800%H>Pci Ints:000124BD%H>Watchdog TO:00000000%H>ErrEnd.%H>%H>STATUS Block @ 0x30134030
In order to understand events and errors which occurred on the system, many times, the inventor has recognized that the is a need to take a look at more than one log file and understand what was happening across the system at that time. Looking for the information at 132 log file is difficult if not impossible. In other words: There is a need for a tool that will reduce the debug time, in order to understand engineering and manufacturing issues.
In accordance with the present invention, the method includes testing each one of the CPUs on each one of the plurality of director printed circuit. Results from such test are collected in a memory of a computer. The results are collected in a predetermined format. The method processes the collected data to present the results of the tests on a display of the computer in a different format. The different format comprises lines of information on the computer display. Each one of the lines of information identifies a corresponding one of the CPUs and indicates whether such corresponding one of the CPUs passed or failed the testing thereof.
In one embodiment, the processing includes presenting the results of the tests as a second set of lines of information on a different view of the computer display. The second set of lines of information identifies each one of the CPUs and the operating states thereof when the plurality of CPUs were tested and operated during a selected, common, period of time.
In one embodiment, the system includes a environmental printed circuit board interconnected to the plurality of director printed circuit boards and the memory printed circuit board through a backplane. The environmental printed circuit board is plugged into a different slot of such backplane. The environmental printed circuit board, the plurality of director printed circuit boards and the memory printed circuit board have thereon sensors for measuring voltages produced on such printed circuit boards and operating temperatures of such printed circuit boards. The environmental printed circuit board has thereon circuitry for producing signals representative of the measured voltages and temperatures during the testing. The method includes: collecting the produced signals in the memory of the computer. The results are collected in a predetermined format. The method processes the collected data to present the results of the tests on a display of the computer in a different format. The different format comprises lines of information on the computer display. Each one of the lines of information identifies a corresponding one of the boards and presents the temperature and voltages of such corresponding one of the boards.
More particularly, the method collects results from such tests in a memory of a computer. The results are collected in a predetermined format, such format comprising a plurality of data structures. Each one of such data structures is associated with a corresponding one of the CPUs. The method processes the collected data from the plurality of data structures to combine the plurality of data structures into a common, linked data structure. The method presents data in the linked data structure on a display of the computer as lines of information. Each one of the lines of information identifies a corresponding one of the CPUs and indicating whether such corresponding one of the CPUs passed or failed the testing thereof. The method presents a second set of lines of information on a different view of the computer display, the second set of lines of information identifying each one of the CPUs and the operating states thereof when the plurality of CPUs were tested and operated during a selected, common, period of time.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.